Universal serial buses (USBs) are generally classified under three standards that specify transfer rates, namely, a low speed (LS) standard for a transfer rate of 1.5 Mbps, a full speed (FS) standard for a transfer rate of 12 Mbps, and a high speed (HS) standard for a transfer rate of 480 Mbps. Data is transferred by transmitting and receiving differential signals between transmission and reception circuits.
The FS standard further specifies a cross voltage Vcross of the differential signals to be in the range of, for example, 1.3 V to 2.0 V with respect to a power supply voltage in the range of 3 V to 3.6 V. Accordingly, a transmission circuit with performance high enough to satisfy the specified cross voltage Vcross needs to be provided.
FIG. 1 illustrates a transmission circuit of the related art, based on the FS standard. The transmission circuit includes an output circuit 1a and an output circuit 1b. Data DP is input to the output circuit 1a and data DM is input to the output circuit 1b. The data DP and DM are differential signals as illustrated in FIG. 3. Further, an enable signal EN and a signal ASEZ with an overbar are input to each of the output circuits 1a and 1b. 
FIG. 2 illustrates a configuration of the output circuit 1a in detail. The data DP is input to a NOR circuit 2 and a NAND circuit 3a. An enable signal EN with an overbar is input to the NOR circuit 2 and the enable signal EN is input to the NAND circuit 3a. The enable signals EN with an overbar and EN are complementary signals.
An output signal of the NOR circuit 2 is input to a NAND circuit 3b. An output signal of the NAND circuit 3a is input to a NAND circuit 3c. The signal ASEZ with an overbar is input to the NAND circuits 3b and 3c. 
An output signal of the NAND circuit 3b is input through a buffer circuit 4a, and inverter circuits 5a and 5b to the gate of an output transistor TP1 that is a P-channel metal oxide semiconductor (PMOS) transistor.
An output signal of the NAND circuit 3c is input through a buffer circuit 4b, and inverter circuits 5c and 5d to the gate of an output transistor TN1 that is an N-channel MOS (NMOS) transistor.
A current limiting circuit 6a is interposed between the inverter circuit 5b and a power supply Vss on the low potential side. The inverter circuit 5b operates as a drive circuit for the output transistor TP1. The current limiting circuit 6a limits a current that flows from the inverter circuit 5b to the power supply Vss. Thus, as illustrated in FIG. 3, a drive signal DPp that is output from the inverter circuit 5b falls slowly.
A current limiting circuit 6b is interposed between the inverter circuit 5d and a power supply VDD on the high potential side. The inverter circuit 5d operates as a drive circuit for the output transistor TN1. The current limiting circuit 6b limits a current that flows from the power supply VDD to the inverter circuit 5d. Thus, as illustrated in FIG. 3, a drive signal DPn output from the inverter circuit 5d rises slowly.
The source of the output transistor TP1 is coupled to the power supply VDD. The drain of the output transistor TP1 is coupled to the drain of the output transistor TN1. The source of the output transistor TN1 is coupled to the power supply Vss.
An output signal FSDP is output from the drains of the output transistors TP1 and TN1 through a resistor R.
In the output circuit 1a configured as described above, when the enable signal EN reaches an “H” level and the enable signal EN with an overbar reaches an “L” level, and the signal ASEZ with an overbar reaches the “H” level, the output signal FSDP of the “H” or “L” level is output based on the data DP.
When the data DP is at the “H” level, the drive signal DPp output from the inverter circuit 5b reaches the “H” level and the output transistor TP1 is turned off, and the drive signal DPn output from the inverter circuit 5d reaches the “H” level and the output transistor TN1 is turned on. As a result, the output signal FSDP reaches the “L” level.
When the data DP is at the “L” level, the drive signal DPp output from the inverter circuit 5b reaches the “L” level and the output transistor TP1 is turned on, and the drive signal DPn output from the inverter circuit 5d reaches the “L” level and the output transistor TN1 is turned off. As a result, the output signal FSDP reaches the “H” level.
Referring to FIG. 3, the rising speed and the falling speed of the output signal FSDP are set to satisfy the FS standard using the current limiting circuits 6a and 6b of the inverter circuits 5b and 5d. 
The output circuit 1b is configured substantially the same as the output circuit 1a. The data DM that is the complementary signal of the data DP are input to the output circuit 1b. Drive signals DMp and DMn, depicted in FIG. 3, are output from the inverter circuits that drive output transistors and the output signal FSDM that is the complementary signal of the output signal FSDP is output.
When the drive capabilities of the output circuits 1a and 1b in the transmission circuit configured as described above are substantially equal, the rising and falling speeds of the output signal FSDP and the rising and falling speeds of the output signal FSDM are substantially equal, as illustrated in FIG. 3. The cross voltage Vcross obtained at the intersection point of the output signals FSDP and FSDM becomes approximately half of the voltage of the power supply VDD to satisfy the FS standard.
However, when variations in the drive capabilities of the PMOS transistor and the NMOS transistor (which are the output transistors of the output circuits 1a and 1b) are caused by process variation, the cross voltage Vcross may fail to satisfy the FS standard.
FIG. 4 illustrates operations performed when the drive capability of the NMOS output transistor of the output circuit 1a or 1b is lower than the drive capability of the PMOS output transistor of the output circuit 1a or 1b. 
As further illustrated in FIG. 4, the rising and falling speeds of the output signal FSDP and the rising and falling speeds of the output signal FSDM are imbalanced and the cross voltage Vcross increases. As a result, the FS standard is not satisfied.
FIG. 5 illustrates operations performed when the drive capability of the PMOS output transistor of the output circuit 1a or 1b is lower than the drive capability of the NMOS output transistor of the output circuit 1a or 1b. 
As further illustrated in FIG. 5, the rising and falling speeds of the output signal FSDP and the rising and falling speeds of the output signal FSDM are imbalanced and the cross voltage Vcross decreases. As a result, the FS standard is not satisfied.
Japanese Patent Application Laid-Open Publication No. 2002-111477 discusses a USB driver for obtaining a crosspoint voltage that satisfies the standard by comparing an output voltage with a reference voltage, and controlling timing of turning on and off an output transistor.
While a USB cable is coupled to an output terminal, the output voltage may vary due to a reflected wave input to the output terminal. Thus, when the reference voltage is not adjusted, depending on the variation in the output voltage, the quality of the output signal waveform may become worse. However, adjusting the reference voltage based on the reflected wave that varies depending on the USB cable is difficult in practice.
Japanese Patent Application Laid-Open Publication No. 2005-191677 discusses a differential output buffer circuit that may adjust the rising and falling speeds of an output signal by adjusting a gate voltage of an output driver using a gate voltage adjusting circuit.
However, the configuration discussed in Japanese Patent Application Laid-Open Publication No. 2005-191677 requires a control circuit for controlling the gate voltage adjusting circuit, and the gate voltage adjusting circuit and the control circuit may become larger in scale for adjusting the gate voltage of the output driver precisely. In addition, costs may increase if it becomes necessary to perform operation tests based on simulations, and if the results of the simulations to control the gate voltage adjusting circuit to cope with the variations in the drive capabilities of the output transistors result in other necessary changes.
Moreover, Japanese Patent Application Laid-Open Publication No. 2003-309460 discusses a USB transceiver for stabilizing a crossover voltage by correcting operations of a prebuffer circuit and compensating for a gate voltage of an output transistor.
However, since a capacitor that feeds back an output voltage is used in Japanese Patent Application Laid-Open Publication No. 2003-309460, the operating speed of the USB transceiver is low and is difficult to use in a transmission circuit that operates based on the FS standard.
In the USB transmission circuit described above, when the drive capabilities of the PMOS transistor and the NMOS transistor in the output circuit become imbalanced due to process variation, it becomes difficult to obtain the cross voltage Vcross that satisfies the FS standard.